In a battery operated product with Liquid Crystal Display (LCD), such as in an electronic pager, a switching-mode power supply (SMPS) is typically employed to produce the LCD contrast voltage (VLCD).
In such a conventional system, VLCD is adjusted by varying a mechanical potentiometer on a contrast voltage feedback connection via a feedback voltage (VFB) input to SMPS. This potentiometer is usually a variable resistor external to SMPS. Alternatively, the LCD contrast voltage can be controlled by varying a reference voltage (VREF) regulated by a pulse width modulated (PWM) signal from the MCU. With the feedback voltage, the SMPS is operated in close-loop mode to generate a base drive voltage for the SMPS which regulates the output to the VLCD. In both such known methods, VLCD is not digitally controlled.
In order to provide a fully digitally controlled LCD contrast voltage, as used in a prior art, a system with a logic control circuit, a counter and a digital-to-analog converter (DAC) have been used. Clock control signals from the MCU are applied to the logic control circuit for generating control signals to the counter. The counter outputs count values to the current-output DAC which also receives a reference voltage from an external reference voltage generator. The output current generated from the DAC draws current and produces a voltage (IR) drop across an external resistor on the VLCD feedback path to SMPS. Operated in closed-loop mode, the SMPS produce a digitally controlled LCD contrast voltage.
However, the quiescent current consumed by the DAC and the reference voltage block is relatively high (in the range of tenths to hundreds of micro-Amperes). It is an object of this invention to provide a circuit for producing a contrast voltage signal for a liquid crystal display in which power consumption may be reduced.